Two cost functions, targeting area and power, are presented . switching activities of an fsm is linked to its power dissipation 引入了以优化面积和功耗为目的的价值函数,并把有限状态机的开关活动性和它的功耗联系在一起。
We investigate the techniques to reduce circuit switch activity, parameter design, dynamic voltage scaling and the simulation environment for verification of the above techniques 研究内容主要关注于减少电路活动性的技术、参数化设计技术、动态电压缩放技术和为衡量这些技术的效果而建立的软硬件仿真环境。
The dynamic power supply current ( iddt ) is a new window through which we can observe the switching activities in digital circuits . iddt testing methods make possible further increasing the fault coverage 动态电流提供了一个观测电路内部开关性能的新的窗口,动态电流测试方法为进一步提高故障覆盖率提供了可能。
By exploring the characters of dynamic power supply currents of digital circuits using spice, this paper analyzed the relation between iddt and the switching activities when a circuit changes from one logical state to another 本文通过spice实验研究数字电路动态电流的特性,分析了数字电路的动态电流与电路逻辑状态转变之间的关系。
Several methods to reduce the circuit switch activity are developed . pre-visiting tag technique is used to reduce the instruction cache activity . base address locality technique is used to reduce the data cache activity 并从减少电路活动性角度出发,开发出减少指令cache功耗的预访问技术,以及减少数据cache功耗的基地址相关技术。
Dynamic power is dominant component of the average power dissipation in cmos circuits . and the value of dynamic power is determined by node capacitance, supply voltage, clock frequency and switching activity of cmos circuits . so most low power designs are achieved by reducing one or more those above parameters 由于cmos电路的功耗与cmos电路的负载电容,电压,时钟频率及开关活动性有关,因此在低功耗cmos触发器设计过程中,许多低功耗设计技术都可以归结到通过减小上面的参数来达到低功耗的目的。